1. Field of the Invention
The invention relates to a method for fabricating semiconductor device, and more particularly, to a method of using HDPCVD process for forming passivation layer on a substrate.
2. Description of the Prior Art
Semiconductor integrated circuits manufactured with Large Scale of Integration (LSI) technologies (LSI, VLSI, ULSI) require a protective layer against mechanical stress and aggressive chemical agents. This layer, generally called “passivation layer” is typically formed by silicon-based dielectrics, such as silicon dioxide (USG), phosphorus-doped or fluorurate-doped silicon oxide (PSG or FSG), silicon nitrides and nitride oxides (Si3N4, SiOx N).
The passivation layer is conventionally formed by means of Chemical Vapor Deposition (CVD) techniques, either Plasma-Enhanced (PECVD) or at Atmospheric Pressure (APCVD).
Final passivation layers formed by means of the above-referred conventional techniques however have some drawbacks. For instance, a temperature mismatch typically results from a flip-chip bonding process and as stress is released from high temperature, phenomenon such as die warpage would result and cause issue such as bump crack. As current technique for fabricating such passivation layer has proven to be unsatisfactory, it is an important task to search for a novel method for resolving the above issue.